1. Field of the Invention
The present invention relates to a clock signal generator for generating a plurality of clock signals with different phases and a clock phase controller using the same, and particularly to a clock signal generator and clock phase controller using the same preferably used for controlling a light emitting device such as a laser diode in an electrophotographic image forming apparatus like a laser printer.
2. Description of Related Art
FIG. 15 is a block diagram showing a configuration of an image output portion of a conventional laser printer. In FIG. 15, the reference numeral 60 designates a pixel pulse generator that receives pixel data Dp in series which are elements of an image and produces a pulse-width modulation signal Pw in response to each of the pixel data Dp; 73 designates a laser diode driver that receives the pulse-width modulation signal Pw and outputs a drive signal; 61 designates a laser diode for emitting a light beam in response to the drive signal; and 62 designates a photoconductive drum on which the beam emitted by the laser diode 61 is thrown so that a latent electrostatic image is formed as the charge distribution corresponding to the scanning of the emitted beam.
The reference numeral 63 designates a pulse control signal generator that receives the serial pixel data Dp and outputs, pixel by pixel, gray scale data Dg and an intra-pixel draw position control signal Sp; 64 designates a fundamental clock generator for generating a fundamental clock signal CLK associated with draw timings of individual pixels by the laser diode 61; 65 designates a level signal generator for generating a level signal Lsg in response to the gray scale data Dg; 66 designates a triangular wave generator that receives the fundamental clock signal CLK and the intra-pixel draw position control signal Sp, and selects one of three triangular waves synchronized with the fundamental clock signal CLK to be output as an output triangular wave Tw; and 67 designates a comparator that compares the output triangular wave Tw with the level signal Lsg, and outputs a pulse-width control signal Pw while the output triangular wave Tw exceeds the level signal Lsg.
Next, the operation of the conventional system will be described.
FIG. 16 is a timing chart showing relationships between various signals of the conventional pixel pulse generator 60. In FIG. 16, the symbol CLK designates the fundamental clock signal CLK; CTRL designates the intra-pixel draw position control signal; 1st-ramp designates a left-hand side triangular wave generated in the triangular wave generator 66, which rises in synchronism with the fundamental clock signal CLK and gradually decreases its level; 2nd-ramp designates a central triangular wave generated in the triangular wave generator 66, which starts a gradual increase in its level in synchronism with the rise of the fundamental clock signal CLK, reaches a peak at around the middle of the period of the fundamental clock signal CLK, and then gradually decreases its level; and 3rd-ramp designates a right-hand side triangular wave generated in the triangular wave generator 66, which gradually increases its level with the fundamental clock signal CLK, and reaches a peak at the next rise of the fundamental clock signal CLK.
Receiving the first fundamental clock pulse CLK at time t1, the triangular wave generator 66 generates the left-hand side triangular wave in response to the intra-pixel draw position control signal Sp, and supplies it to the comparator 67 as the output triangular wave. At the same time, the level signal generator 65 supplies the comparator 67 with the level signal Lsg corresponding to the gray scale data Dg. The comparator 67 compares the left-hand side triangular wave with the level signal Lsg, and outputs the pulse-width control signal Pw in response to the compared result from the rise time t1 of the fundamental clock signal CLK. Thus, the laser diode 61 emits the beam during the high level of the pulse-width control signal Pw so that the charge distribution changes at an upstream portion of the first pixel draw region on the photoconductive drum 62, while the emitted beam scans the photoconductive drum 62.
Receiving the second fundamental clock pulse CLK at time t2, the triangular wave generator 66 generates the central triangular wave in response to the intra-pixel draw position control signal Sp. The comparator 67 compares the central triangular wave with the level signal Lsg before and after the center of the fundamental clock pulse CLK, and outputs the pulse-width control signal Pw in response to the compared result. Thus, the charge distribution changes at the central portion of the first pixel draw region on the photoconductive drum 62.
Likewise, at time t3 when the third fundamental clock pulse CLK is generated, the right-hand side triangular wave is compared with the level signal Lsg, and the charge distribution changes at the downstream portion of the first pixel draw region on the photoconductive drum 62. Subsequently, at time t4 when the fourth fundamental clock pulse is generated, the left-hand side triangular wave is compared with the level signal Lsg, and the charge distribution changes at the upstream portion of the second pixel draw region on the photoconductive drum 62.
In this way, the charge distribution, that is, a latent electrostatic image is formed on the photoconductive drum 62 in response to the pulse-width control signal Pw. The image forming apparatus forms at a high speed a high resolution, high gradation output image based on the latent electrostatic image.
The conventional pixel pulse generator 60, however, cannot be implemented as an integrated circuit through a CMOS process because it includes the triangular wave generator 66 consisting of an analog circuit.
In view of this, it will be possible to generate the pulse-width modulation signal by a phase conversion circuit as shown in FIG. 17, which consists of only digital circuit components and hence can be formed through the CMOS process. In FIG. 17, the reference numeral 68 designates an input terminal to which a high frequency clock signal Ch with a frequency of an integer multiple of the fundamental clock signal CLK is applied; 69 designates a counter to which the high frequency clock signal is input along with a reset signal Rst and a phase set signal Pst; 70 designates an AND gate that ANDs the high frequency clock signal Ch and the output Ct of the counter 69; 71 designates a frequency divider for dividing the output of the AND gate 70 so that its output period becomes equal to the period of the fundamental clock signal CLK; and 72 designates an output terminal for producing the output of the frequency divider 71 as the phase converted clock signal Cp.
Next, the operation of the conventional circuitry as shown in FIG. 17 will be described.
FIG. 18 is a timing chart illustrating relationships between various signals of the phase conversion circuit when the phase set signal is set at "3". The counter 69 starts counting of the high frequency clock signal Ch when the reset signal Rst is removed in synchronism with the fundamental clock signal CLK. When the count value reaches "3", the counter 69 changes the output Ct to a high level so that the AND gate 70 starts to output the high frequency clock signal Ch. Then, the frequency divider 71 divides the high frequency clock signal Ch such that its period becomes equal to the period of the fundamental clock signal CLK, and outputs it as the phase converted clock signal Cp.
As a result, the phase conversion circuit can output the phase converted clock signal Cp whose phase is shifted by an amount corresponding to three high frequency clock pulses with respect to the fundamental clock signal CLK.
However, the following problems arises from applying such a phase conversion circuit to a today's image forming apparatus that must meets the demand of producing high gradation (of more than 256 gray levels), high resolution images at a high speed. First, a very high frequency is required of the high frequency clock signal Ch. In addition, this requires fast-response counter, AND gate and frequency divider that can operate quickly in response to the high frequency clock signal Ch. Thus, the conventional phase conversion circuit is not always suitably applicable to the image forming apparatus.